lmh0071
LMH0341, LMH0041, LMH0071, LMH0051
3 Gbps, HD, SD, DVB-ASI SDI Deserializer withLoopthrough and LVDS Interface
General Description
The LMH0341 3 Gbps SDI Deserializer is part of National’sfamily of FPGA-Attach SER/DES products supporting 5-bitLVDS interfaces with FPGAs. When paired with a host FPGAthe LMH0341 automatically detects the incoming data rateand decodes the raw 5-bit data words compliant to any of thefollowing standards: DVB-ASI, SMPTE 259M, SMPTE 292M,or SMPTE 424M. The interface between the LMH0341 andthe host FPGA consists of a 5-bit wide LVDS bus, an LVDSclock and an SMBus interface. No external VCOs or clocksare required. The LMH0341 CDR detects the frequency fromthe incoming data stream, generates a clean clock and trans-mits both clock and data to the host FPGA. The LMH0341,LMH0041 and LMH0071 include a serial reclockedloopthrough with integrated SMPTE compliant cable driver.Refer to table 1 for a complete listing of single channel dese-rializers offered in this family.
The FPGA-Attach SER/DES product family is supported by asuite of IP which allows the design engineer to quickly developvideo applications using the SER/DES products. The productis packaged in a physically small 48 pin LLP package.
Key Specifications
■Output compliant with SMPTE 259M-C, SMPTE 292M,
SMPTE 424M and DVB-ASI
■Typical power dissipation: 590 mW (loopthrough disabled,3G datarate)
■0.6 UI Minimum Input Jitter Tolerance
Features
■■■■■■■
5–bit LVDS Interface
No external VCO or clock required
Reclocked serial loopthrough with Cable DriverPowerdown Mode
3.3V SMBus configuration interfaceSmall 48 pin LLP package
Industrial Temperature range:-40°C to +85°C
Applications
■SDI interfaces for:
————
Video CamerasDVRs
Video Switchers
Video Editing Systems
General Block Diagram
30017201
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2008 National Semiconductor Corporation300172www.national.com
LMH0341, LMH0041, LMH0071, LMH0051Pin Descriptions
Pin NameRX[4:0]+RX[4:0]-RXCLK+RXCLK-Serial Data InputsRXIN0+RXIN0-RXIN1+RXIN1-TXOUT+TXOUT-SMBus InterfaceSDASCKSMB_CS
I/O, LVCMOSInput, LVCMOSInput, LVCMOS
SMBus Data I/O PinSMBus Clock Input PinSMBus Chip Select Input PinDevice is selected when High.Reset Input PinH = normal modeL = device in RESETPLL LOCK Status OutputH = unlock conditionL = PLL is Locked
DVB_ASI Select Input
H = DVB_ASI Mode enabledL = Normal Mode enabled
Loopthrough enable Input
H=Reclocked Loopthrogh activeL=Reclocked Loopthrough disabledInput multiplexer selectH=RXIN1 selectedL=RXIN0selected
General Purpose Input / OutputSoftware configurable I/O pins.Configuration Input – Must tie HighPull High via 5 kΩ resistor to VDD3V3
Input, DifferentialInput, Differential
Serial differential input PinsChannel 0
Serial differential input PinsChannel 1
Serial Digital Interface Output PinNon-Inverting Output
Serial Digital Interface Output PinInverting Output
TypeOutput, LVDSOutput, LVDS
Description
LVDS Data Output Pins
Five channel wide DDR interface.LVDS Clock Output PinsDDR Interface.
LVDS Input Interface
Loopthrough Serial Output
Output, CMLOutput, CML
Control and Configuration PinsRESETInput, LVCMOS
LOCKOutput, LVCMOS
DVB_ASIInput, LVCMOS
Loopthru_ENInput, LVCMOS
RX_MUX_SELInput, LVCMOS
GPIO[2:0]RSVD_H
I/O, LVCMOSInput, LVCMOS
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LMH0341, LMH0041, LMH0071, LMH0051Pin NameAnalog InputsRSET
TypeInput
Description
Serial Loopthrough Output Amplitude Control
Resistor connected from this pin to ground to set the signal amplitude. Nominally8.06kΩ for 800mV output (SMPTE).Loop Filter ConnectionLoop Filter Reference
Do Not Connect – Leave Open3.3V Power Supply connection3.3V PLL Power Supply connection2.5V Power Supply connection
Ground connection – The DAP (large center pad) is the primary GND connectionfor the device and must be connected to Ground along with the GND pins.
TABLE 1. Feature Table
LF_CPLF_REFDNCVDD3V3VDDPLLVDD2V5GND
Input PowerPowerPowerGround
Power Supply and Ground
DeviceLMH0341LMH0041LMH0071LMH0051
SMPTE 424M SupportSMPTE 292M SupportSMPTE 259M SupportDVB-ASI SupportActive Loopthrough
×
×× ×
××××
××××
×××
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LMH0341, LMH0041, LMH0071, LMH0051Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (VDD3V3)Supply Voltage(VDD2V5)LVCMOS input voltageLVCMOS output voltageSMBus I/O Voltage
−0.3V to +4.0V—0.3V to +3.0V
−0.3V to (VDD3V3+0.3V)−0.3V to (VDD3V3+0.3V)
—0.3V to +3.6V
LVDS Input VoltageJunction TemperatureStorage Temperature
Lead Temperature—Soldering 4 secondsThermal Resistance—
Junction to Ambient—θJA
ESD Rating—Human Body Model, 1.5 KΩ, 100 pF
0.3V to 3.6V
+150°C−65° to 150°C
+260°C
26°C/W
≥±8KV
Recommended Operating Conditions
Parameter
Supply Voltage (VDD3V3-GND)Supply Voltage (VDD2V5-GND)
Supply noise amplitude (10 Hz to 50 MHz)Ambient TemperatureCase Temperature
Input Data Rate — LMH0341Input Data Rate — LMH0041Input Data Rate — LMH0071Input Data Rate — LMH0051
LVDS PCB board trace length (mismatch <2%)RSTERM — SMBus termination resistor value
Loopthrough Output Driver Pullup Resistor Termination Voltage
Min3.1352.375 −40 270270270270
Typ3.32.5 +25 10002.5
Max3.4652.625100+8510229701485270148525 2.625
UnitsVVmVP-P°C°CMbpsMbpsMbpsMbpscmΩV
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LMH0341, LMH0041, LMH0071, LMH0051Electrical Characteristics
SymbolIDD2.5
Parameter
Over supply and Operating Temperature ranges unless otherwise specified. (Note 2)
Condition
2.97 GbpsLT off1.485 GbpsLT off(Note 9)270 MbpsLT off(Note 9)2.97 GbpsLT on1.486 GbpsLT on(Note 9)270 MbpsLT on(Note 9)
2.5V supply current for LMH0051
IDD3.3
3.3V supply current for LMH0341,LMH0041, LMH0071
3.3V supply current for LMH0051
PD
Power Consumption
1.485 Gbps270 MbpsLT off(Note 9)LT on(Note 9)
2.97 Gbps, loopthrough enabled1.485 Gbps, loopthroughenabled(Note 9)270 Mbps, Loopthroughenabled(Note 9)2.97 Gbps, LoopthroughDisabled(Note 9)1.485 Gbps, LoopthroughDisabled(Note 9)270 Mbps, LoopthroughDisabled(Note 9)
Min
Typ6752409984655240106112106617580532517480450
Max77594610892715946120127119710670620610560530
UnitsmAmAmAmAmAmAmAmAmAmAmAmWmWmWmWmWmW
2.5V supply current for LMH0341,LMH041, LMH0071
Control Pin Electrical Characteristics
SymbolVIHVILVOHVOLVCLIIN
Parameter
High Level Input VoltageLow Level Input VoltageHigh Level Output VoltageLow Level Output VoltageInput Clamp VoltageInput Current
Over supply and Operating Temperature ranges unless otherwise specified. Applies to DVB_ASI,RESET and LOCK,GPIO Pins,RX_MUX_SEL, Loopthru_EN(Note 2)
Condition
Min2.0
IOH = −0.4 mAIOH = −2 mAIOL = 2 mAICL = −18 mA
VIN = 0.4V, 2.5V or VDDPullupand pulldown resistors notenabled.VOUT = 0V
−0.32.72.7 —40
Typ 3.253.20.10.9
MaxVDD3V3+0.30.8 0.3−1.540
UnitsVVVVVVμA
IOS
Output Short Circuit Current —44 mA
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LMH0341, LMH0041, LMH0071, LMH0051SDI Input Electrical Characteristics
SymbolVIDIINRITTOLJIT
Parameter
Input Differential VoltageInput CurrentInput TerminationInput Jitter Tolerance
Over supply and Operating Temperature ranges unless otherwise specified. (Note 2)
Condition
DC Coupled, VCM = 0.05V toVDD-0.05V(Note 7)0V < VIN < 2.4V
Frequency < f2 (From SMPTERP 184)Frequency Jitter Transfer Function3 dB loop bandwidthJitter PeakingInput Return Loss Figure 7Figure 7 Measured on 'ALP' evaluationboard(Note 7) Min230−30084 Typ 10060.60.130.05>25dB to1.5GHz>12dB to3 GHz Max220050116 UnitsmVµAΩUIUIFraction ofDatarate dBdB www.national.com6 LMH0341, LMH0041, LMH0071, LMH0051LVDS Output Electrical Characteristics SymbolVODΔVODVOSΔVOSIOS Parameter Differential Output VoltageChange in VOD between complementary output statesOffset Voltage Change in VOS between complementary output statesOutput Short Circuit Current RL = 100Ω Over supply and Operating Temperature ranges unless otherwise specified. (Note 2) Condition Min230 1.125 VOUT = 0V, RL = 100Ω —50 Typ 1.25 Max310351.37535 UnitsmVmVVmVmA LVDS Switching Characteristics SymboltROTRtROTFtROCP Parameter LVDS Low to High Transition timeLVDS High to Low Transition timeReceiver output clock period Over supply and Operating Temperature ranges unless otherwise specified. (Note 2) Condition See LVDS Switching timesRxCLKOUT is DDR. If divide by4 is enabled, the output clockperiod will be doubled See Receiver timingspecifications Min Typ3003002T Max Unitspspsns tRODCtROCHtROCLtRBITtDVBCtDVACtROJR RxCLKOUT Duty CycleRxCLKOUT high timeRxCLKOUT low timeReceiver output bit width 451.511.51 650650 50 T 2.5 55 %nsnsnspspsps RX data transition to RXCLK transitionSee Receiver timingRXCLK transition to RX data transitionspecifications(Note 8)Receiver output Random Jitter Receiver output intrinsicrandom jitter. Bit error rate ≤ 10-15. Alternating10 pattern. RMS(Note 7) tROJTtRDtRLA Peak-to-Peak Receiver Output JitterReceiver Propagation DelayReceiver Link Acquisition Time (Note 7) See Receiver (LVDS Interface)Propagation Delay From device reset or change ininput data rate to lockedcondition LVDS Differential Output Skewbetween + and − pins 7012 T 125 24 ps ms tLVSK LVDS Output Skew 20 ps 30017202 FIGURE 1. LVDS Switching Times 7 www.national.com LMH0341, LMH0041, LMH0071, LMH0051SMBus Input Electrical Characteristics SymbolVSILVSIHVSDDVOLISLEAKBISLEAKPCSI Parameter Data, Clock Input Low VoltageData, Clock Input High VoltageNominal Bus VoltageOutput Low voltage Input Leakage per bus segmentInput Leakage per pinCapacitance for SMBdata andSMBclk IOL=2mASee (Note 3) Over supply and Operating Temperature ranges unless otherwise specified. (Note 2) Condition Min 2.12.375 −200−10 Typ Max0.8VSDD3.4650.32001010 UnitsVVVVμAμApF SCK and SDA pinsSee (Notes 3, 4) SMBus Switching Characteristics SymbolfSMBtBUFtSU:CStH:CStHD:STA Parameter Bus Operating Frequency Bus free time between stop and start condition Minimum time between SMB_CSbeing active and Start condition Over supply and Operating Temperature ranges unless otherwise specified. (Note 2) Condition Min104.7301004.0 Typ Max100 UnitskHzμsnsnsμs (Note 7) Minimum time between stop condition(Note 7)and releasing SMB_CS Hold time after (repeated) startcondition. After this period, the firstclock is generated Repeated Start condition setup timeStop Condition setup timeData hold timeData setup timeClock Low PeriodClock high time Time in which a device must beoperational after power on At ISPULLUP = MAX tSU:STAtSU:STOtHD:DATtSU:DATtLOWtHIGHtPOR 4.74.03002504.74.0 50500 μsμsnsnsμsμsms 30017205 FIGURE 2. SMBus Timing Parameters www.national.com8 LMH0341, LMH0041, LMH0071, LMH0051SDI Output Switching Characteristics (LMH0341 / LMH0041 / LMH0071) Over supply and Operating Temperature ranges unless otherwise specified. (Note 2)Symbol tr Parameter SDI Output DatarateSDI Output Rise Time DR=2.97 Gbps(Note 7)DR=1.485 Gbps(Note 7)DR=270 Mbps(Note 7) tf SDI Output Fall Time DR=2.97 Gbps(Note 7)DR=1.485 Gbps(Note 7)DR = 270 Mbps(Note 7) Δtt Mismatch between Rise and Falltimes Propagation Delay LatencyPeak to Peak Output Jitter 2.97 Gbps(Note 7)1.485 Gbps(Note 7)270 Mbps(Note 7) tSDtJ 2.97 Gbps(Notes 7, 6)1.485 Gbps(Notes 7, 6)270 Mbps(Notes 7, 6) VODRLtOS SDI Output Voltage(LoopthroughOutput) Output Return LossOutput Overshoot Into 75Ω Load Measured 5 MHz to 1483 MHz(Note 7)(Note 7) Condition Min270 400 400 720 Typ tCIP25356580015 Max2970135145100013514510002530100 4050110880 5 UnitsMHzps pspspspspspsns mVdB% Note 1:“Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. It is not implied that the device will operate upto these limits. Note 2:Typical Parameters measured at VDD=3.3V, TA=25°C. They are for reference purposes and are not production tested.Note 3:Recommended value—Parameter is not tested. Note 4:Recommended maximum capacitance load per bus segment is 400 pF.Note 5:Maximum termination voltage should be identical to the device supply voltage.Note 6:Measured in accordance with SMPTE RP184.Note 7:Specification Guaranteed by characterization Note 8:Specification Characterized at 2.97 Gbps, 1.485 Gbps and 270 Mbps, production tested at 270 Mbps onlyNote 9:Specification Guaranteed by Characterization for LMH0341, other variants production tested 30017204 FIGURE 3. Receiver (LVDS Interface) Propagation Delay 9www.national.com LMH0341, LMH0041, LMH0071, LMH0051Functional Description DEVICE OPERATION The DES is used in digital video signal origination equipment.It is intended to be operated in conjunction with an FPGA hostwhich processes data received by the SER, and converts thefive bit output data to an appropriate parallel video format —usually 10 or 20 bits wide. In most applications, the input datato the DES will be data compliant with DVB ASI, SMPTE259M-C, SMPTE 292M or SMPTE 424M, and the decodingwill be done by the IP provided by National Semiconductor orsimilar IP to result in a decoded output. National Semicon-ductor offers IP in source code format to perform the appro-priate decoding of the data, as well as evaluation platforms toassist in the development of target applications. For more in-formation please contact your local National SemiconductorSales Office/Distributor POWER SUPPLIES The DES has several power supply pins, at 2.5V as well as3.3V. It is important that these pins all be connected, andproperly bypassed. Bypassing should consist of parallel4.7μF and 0.1μF capacitors as a minimum, with a 0.1μF ca-pacitor on each power pin. The device has a large contact inthe center of the bottom of the package. This contact must beconnected to the system GND as it is the major ground con-nection for the device. A 22 μF capacitor is required on theVDDPLL pin which is connected to the 3.3V rail Discrete bypassing is ineffective above 30 MHz to 50 MHz inpower plane-based distribution systems. Above this frequen-cy range, the intrinsic capacitance of the power-ground sys-tem can be used to provide additional RF bypassing. To makethe best use of this, make certain that there are PCB layersdedicated to the Power supplies and to GND, and that theyare placed next to each other to provide a distributed capac-itance between power and GND. The DES will work best when powered from linear regulators.The output of linear regulators is generally cleaner with lessnoise than switching regulators. Output filtering and powersystem frequency compensation are generally simpler andmore effective with linear regulators. Low dropout linear reg-ulators are available which can usually operate from lowerinput voltages such as logic power supplies, thereby reducingregulator power dissipation. Cascading of low dropout regu-lators should not be done since this places the entire supplycurrent load of both load systems on the first regulator in thecascade and increases its loading and thermal output.POWER UP The 3.3V power supply should be brought up before the 2.5Vsupply. The timing of the supply sequencing is not important.The device has a power on reset sequence which takes placeonce both power supplies are brought up. This sequence willreset all register contents to their default values, and will placethe PLLs into link acquisition mode, attempting to lock on theRXIN0input. RESET There are three ways in which the device may be reset. Thereis an automatic reset which happens on power-up; there is areset pin, which when brought low will reset the device, withnormal operation resuming when the pin is driven high again.The third way to reset the device is a soft reset, implementedvia a write to the reset register. This reset will put all of theregister values back to their default values, except it will not affect the address register value if the SMBus default addresshas been changed. LVDS OUTPUTS The DES has LVDS outputs, compatible with ANSI/TIA/EIA-644. LVDS outputs expect to drive a 100Ω transmissionline which is properly terminated at the host FPGA inputs. Itis recommended that the PCB trace between the FPGA andthe receiver be less than 25 cm. Longer PCB traces may in-troduce signal degradation as well as channel skew whichcould cause serialization errors. The LVDS outputs on the DES have a programmable outputswing. The default condition is for the smaller size swing, inorder to save power. If a larger amplitude output swing is de-sired, this can be effected through the use of register 0x27hLVDS OUTPUT TIMING The DES output timing, in it's default condition, is describedin the LVDS Switching characteristics table. The user has theability to adjust the LVDS output timing to make it easier tolatch into the host FPGA if desired. This is done via register0x28h where both the clock to data timing may be adjusted,as well as changing the RXCLK from being a DDR clock to aclock at the rate of DDR/2 LOOP FILTER The DES has an internal PLL which is used to recover theembedded clock from the input data. The loop filter for thisPLL has external components, and for optimum results inSerial Digital Interface applications, a capacitor and a resistorin series should be connected between pins 26 and 27 asshown in the typical interface circuit. DVB-ASI MODE DVB-ASI mode is enabled when the DVB-ASI pin is broughtto a high state. When the DVB-ASI mode is enabled, an in-ternal framer and 8b10b decoder is engaged such that thedata appearing on RX0-RX3 will represent a nibble of the de-coded 8b10b data. RX4 is an Idle character detect and canbe used as an enable to allow the receiver to not write datainto an external FIFO. RX4 is high if the data being presentedon RX0-RX3 represents the idle character. The Most Signifi-cant Nibble of data is presented on the rising edge of RXCLK,and the least significant on the falling edge of RXCLK.SDI INPUT INTERFACING The device has two inputs, one of which is selected via amultiplexer with the RX_MUX_SEL pin. Whichever input isselected will be routed to the clock recovery portion of thedeserializer, and once it is reclocked, the signal will be fed tothe loopthrough outputs. Most SDI interfaces require anequalizer to meet performance requirements. For HD-SDIand SD-SDI applications, the LMH0044 is an ideal equalizerto use for this. The LMH0044 is packaged in a small compactpackage and the outputs can be connected directly to theRXIN inputs of the LMH0041. The LMH0344 is pin compatiblewith the LMH0044 and will support 3 Gbps data, making it anideal choice to accompany the LMH0341. www.national.com10 LMH0341, LMH0041, LMH0071, LMH0051but the typical interface circuit shows values that would be agood starting point. 30017207 30017206 FIGURE 5. Simplified SDI Output Circuit FIGURE 4. Simplified SDI Input Circuit SWITCHING SDI INPUTS When the input to the DES is switched from one source toanother, either via the internal 2:1 multiplexor on the inputs,or via an external crosspoint switch, there are a variety of be-haviors possible If the input switch is between two signalsoperating at the same datarate, then in most cases, the DESwill not lose lock. There will be a small number of words withcorrupted data as the PLL slews it's phase to match the newinput signal. Under some circumstances (dependent onphase difference between the inputs, temperature, etc) it ispossible that the PLL will lose lock, and then reacquire lock.This condition can be seen by monitoring the LOCK pin wherea high going pulse will indicate a loss of lock condition. If aloss of lock happens, it will be for a time period of approxi-mately 5ms before lock is reattained. In the invent that theswitch on the input is between signals at different datarates— for example from a 270 Mbps signal to a 1.485 Gbps input,then the lock procedure is much more complex, and the locktime will be significantly longer. In either case, the IP that isprocessing the received signal will need to reestablish theproper framing of the words. SDI OUTPUT INTERFACING The serial loopthrough outputs provide low-skew comple-mentary or differential signals. The output buffer is a currentmode design, and as such has a high impedance output. Todrive a 75Ω transmission line, a 75Ω resistor from each of theoutput pins to VDD2V5 should be connected. This resistor hastwo functions—it converts the current output to a voltage,which is used to drive the cable, and it acts as the back ter-mination resistor for the transmission line. The output driverautomatically adjusts its slew rate depending on the inputdatarate so that it will be in compliance with SMPTE 259M,SMPTE292M or SMPTE 424M as appropriate. In addition tooutput amplitude and rise/fall time specifications, the SMPTEspecs require that SDI outputs meet an Output Return Loss(ORL) specification. There are parasitic capacitances that willbe present both at the output pin of the device and on theapplication printed circuit board. To optimize the return loss,these must be compensated for, usually with a series networkcomprising a parallel inductor and resistor. The actual valuesfor these components will vary from application to application, JITTER MANAGEMENT SMPTE 424M (the 3 Gbps standard) relaxed the require-ments of SDI transmitters from 0.2UI to 0.3UI, which meansthat the challenge of receiving these signals error free is verydifficult. The parameter of importance to determine if the DESwill be able to receive the signal error free is the Jitter Toler-ance. Figure 8 shows the LMH0341 Jitter tolerance curve witha 2.97 Gbps input — any signal which has less jitter than whatis on the upper curve of this figure will be able to be receivedby the DES. The lower line in the curve shows the SMPTErequirement for any receiver. There is a slight dip in the levelat frequencies abive about 10MHz which is an artifact of thetest equipment that was used to capture the data. Once thesignal is received, the next concern as far as jitter goes is howmuch of the jitter that was on the input signal will be passedthrough to the RXCLK output. This is answered by the Jittertransfer characteristics. The Jitter transfer function is the ratioof the input jitter to the output jitter, measured as a function offrequency. The specification tables show two of the parame-ters related to this curve — δ is the jitter peaking and indicateswhat the maximum gain of the jitter is. Ideally δ is 0, but alower number is better. If several devices are used in a sys-tem, and the frequency at which δ is maximum is the samefor all of them, then the gains will multiply, and there is a riskthat there will be excessive jitter accumulating at that fre-quency. The LMH0341 has very low Jitter peaking, so thisshould not be a concern. The other parameter of interest isλ which is the jitter transfer bandwidth. Jitter on the input atthe frequency λ is attenuated by 3dB, and any jitter at fre-quencies greater than λ is attenuated by more than this. Froma design standpoint, it means that you primarily only need toworry about the jitter at frequencies below λ. The LMH0341adjusts it's loop bandwidth dependent on datarate, so for thelower datarates, it has a lower loop bandwidth.Figure 8 showsthe jitter transfer curve of an LMH0341 with a 2.97 Gbps signalinput, 0.5UI of input jitter, and nominal power supplies andtemperature. 11www.national.com LMH0341, LMH0041, LMH0071, LMH0051tolerant. The use of the SMB_CS signal is recommended forapplications with multi-drop applications (multiple devices toa host). The System Management Bus (SMBus) is a two wire interfacedesigned for the communication between various systemcomponent chips. By accessing the control functions of thecircuit via the SMBus, pin count is kept to a minimum whileallowing a maximum amount of versatility. The SMBus hasthree pins to control it, there is an SMBus CS pin which en-ables the SMBus interface for the device, a Clock and a Dataline. In applications where there might be several devices, theSDA and SCK pins can be bussed together and the individualdevices to be communicated with may be selected via the CSpin The SCL and SDA are both open drain and are pulled highby external pullup resistors. The DES has several internalconfiguration registers which may be accessed via the SM-Bus. These registers are listed inDES Register Detail Table . 30017221 FIGURE 6. Jitter Tolerance Curve Transfer Of Data To The Device Via The SMBus During normal operation the data on SDA must be stable dur-ing the time when SCK is high. START / STOP / IDLE conditions— There are three unique states for the SMBus: STARTA HIGH to LOW transition on SDA while SCK is high indicates a message START condition, STOPA LOW to HIGH transition on SDA while SCK is high indicates a message STOP condition. IDLEIf SCK and SDA are both high for a time exceeding tBUF from the last detected STOP condition or if theyare high for a total exceeding the maximum specifi-cation for tHIGH then the bus will transfer to the IDLEstate.SMBus Transactions A transaction begins with the host placing the DES SMBusinto the START condition, then a byte (8 bits) is transferred,MSB first, followed by a ninth ACK bit. ACK bits are ‘0’ to sig-nify an ACK, or ‘1’ to signify NACK, after this the host holdsthe SCL line low, and waits for the receiver to raise the SDAline as an ACKnowledge that the byte has been received.WRITING TO REGISTERS VIA THE SMBus INTERFACETo write a data value to a register in the DES, the host writesthree bytes, the first byte is the device address—the deviceaddress is a 7 bit value, and if writing to the DES the last bit(LSB) is set to ‘0’ to signify that the operation is a write. Thesecond byte written is the register address, and the third bytewritten is the data to be written into the addressed register. Ifadditional data writes are performed, the register address isautomatically incremented. At the end of the write cycle thehost places the bus in the STOP state. READING FROM REGISTERS VIA THE SMBusINTERFACE To read the data value from a register, first the host writes thedevice address with the LSB set to a ‘0’ denoting a write, thenthe register address is written to the device. The host thenreasserts the START condition, and writes the device addressonce again, but this time with the LSB set to a ‘1’ denoting aread, and following this the DES will drive the SDA line withthe data from the addressed register. The host indicates thatit has finished reading the data by asserting a ‘1’ for the ACKbit. After reading the last byte, the host will assert a ‘0’ forNACK to indicate to the DES that it does not require any moredata. 30017213 FIGURE 7. Jitter Transfer Curve Parameters 30017220 FIGURE 8. Jitter Transfer Curve SMBus INTERFACE The configuration bus conforms to the System ManagementBus (SMBus) 2.0 specification. SMBus 2.0 includes multipleoptions. The optional ARP (Address Resolution Protocol) fea-ture is not supported. The I/O rail is 3.3V only and is not 5V www.national.com 12 LMH0341, LMH0041, LMH0071, LMH005130017215 FIGURE 9. SMBus Configuration 1 — Host to single device 30017216 FIGURE 10. SMBus Configuration 2 — Host to multiple devices with SMB_CS signals 30017217 FIGURE 11. SMBus Configuration 3 — Host to multiple devices with multiple SMBus Interfaces 13www.national.com LMH0341, LMH0041, LMH0071, LMH0051GENERAL PURPOSE I/O PINS (GPIO) The DES has three pins which can be configured to providedirect access to certain register values via a dedicated pin.For example if a particular application required fast action tothe condition of the deserializer losing it’s input signal, thePCLK detect status bit could be routed directly to an externalpin where it might generate an interrupt for the host processor.GPIO pins can be configured to be in TRI-STATE®TRI-STATE (High Impedance) mode, the buffers can be disabled,and when used as inputs can be configured with a pullup re-sistor, a pulldown resistor or no input pin biasing at all. Each of the GPIO pins has a register to control it. For each ofthese registers, the upper 4 bits are used to define what func-tion is desired of the GPIO pin with options being slightlydifferent for each of the three GPIO pins. The pins can beused to monitor the status of various internal states of theLMH0040 device, to serve as an input from some externalstimulus, and for output to control some external function.GPIO0 Functions Allow for the output of a signal programmed by the SMBusAllow the monitoring of an external signal via the SMBusMonitor the status of the signal on input 0GPIO1 Functions Monitor Power On Reset Allow for the output of a signal programmed by the SMBusAllow the monitoring of an external signal via the SMBusMonitor the status of the signal on input 1 Monitor Lock condition of the input clock recovery PLLGPIO2 Functions Allow for the output of a signal programmed by the SMBusAllow the monitoring of an external signal via the SMBusProvides a constant clock signalLVDS TX Clock at 1/20 full rateCDR Clock at 1/20 full rate Bits 2 and 3 are used to determine the status of the internalpullup/pulldown resistors on the device—they are loaded ac-cording to the following truth table:00: pullup and pulldown disabled01: pulldown enabled10: pullup enabled11: reserved Bit 1 is used to enable or disable the input buffer. If the GPIOpin is to be used as an output pin, then this bit must be set toa ‘0’ disabling the output. The LSB is used to switch the output between normal outputstate and high impedance mode. If the GPIO is to be used asan input pin, this bit must be set to ‘0’ placing the output inhigh Z mode. As an example, if you wanted to use the GPIO0 pin to monitorthe status of the input signal on input 0, you would load reg-ister 02h with the value 0010 0001b 30017208 FIGURE 12. Simplified LVCMOS Input Circuit 30017209 FIGURE 13. Simplified LVCMOS Output CircuitPOTENTIAL APPLICATIONS FOR GPIO PINS In addition to being useful debug tools while bringing a DESdesign up, there are other practical uses to which the GPIOpins can be put: Automatic Switching To Secondary Input If The Signal OnThe Primary Input Is Lost By setting GPIO0 to monitor the status of input0 when thereis a signal present on input 0, the GPIO0 pin will go low whenthere is no signal present on the Input0 pin, if this signal isinverted and then used to drive the RX_MUX_SEL then if theinput on Input0 is lost, the device will automatically switch toInput1. Another possible use of the GPIO pins is to provide access toexternal signals such as the CD output from an equalizer orthe LOCK output from the DES itself via the SMBus, helpingto minimize the number of connections between the DES andthe FPGA. www.national.com14 LMH0341, LMH0041, LMH0071, LMH0051Application Information PCB LAYOUT RECOMMENDATIONS In almost all applications, the inputs to the DES will be drivenby the output of an equalizer such as the LMH0044. Youshould follow the recommendations on the equalizerdatasheet for the interface between the input connector andthe equalizer—the DES will be placed between the equalizerand the FPGA. If the DES is too close to the equalizer, thenthere is a risk of crosstalk between the high speed digital out-puts of the DES and the equalizer inputs. Conversely, if toofar away then the interconnect between the equalizer and theDES may either pick up stray noise, or may broadcast noisesince this is a very high speed signal. Be certain to treat thesignal from the equalizer to the DES as a differential trace. Ifthere is skew between the two conductors of the differentialtrace, not only might this cause difficulties for the DES receivecircuitry, but having a phase difference between the sides ofthe pair makes the signal look and radiate like a commonmode signal. If the loopthrough output is going to be used, it is advised thatthe DES be placed close to the Loopthrough output BNC con-nector, and the equalizer be placed close to the SDI InputBNC connector. This will minimize the lengths of the mostcritical connections. The DES includes a cable driver for the loopthrough output.The SMPTE Serial specifications have very stringent require-ments for output return loss on drivers. The output return losswill be degraded by non-idealities in the connection betweenthe DES and the output connector. All efforts should be takento minimize the trace lengths for this area, and to assure thatthe characteristic impedance of this trace is 75Ω. The 75Ωtermination resistor should be placed as close to theloopthrough output pin as is practicable. It is recommended that the PCB traces between the hostFPGA and the DES be no longer than 10 inches (25cm) andthat the traces be routed as differential pairs, with very tightmatching of line lengths and coupling within a pair, as well asequal length traces for each of the six pairs. PCB DESIGN DO’S AND DON’TS DO Whenever possible dedicate an entire layer to each powersupply whenever possible—this will reduce the inductance inthe supply plane. DO use surface mount components whenever possible.DO place bypass capacitors close to each power pin. DON’T create ground loops—pay attention to the cutouts thatare made in your power and ground planes to make sure thatthere are not opportunities for loops. DON’T allow discontinuities in the ground planes—return cur-rents will follow the path of least resistance—for high fre-quency signals this will be the path of least inductance. DO place the Loopthrough outputs as close as possible to theedge of the PCB where it will connect to the outside world.DO make sure to match the trace lengths of all differentialtraces, both between the sides of an individual pair, and frompair to pair. DO remember that VIAs have significant inductance—whenusing a via to connect to a power supply or ground layer, twoin parallel are better than one. DO connect the slug on the bottom of the package to a solidGround connection. This contact is used for the major GNDconnection to the device as well as serving as a thermal viato keep the die at a low operating temperature. 30017219 FIGURE 14. Evaluation Board Loopthrough Output Return LossTYPICAL SMPTE APPLICATIONS CIRCUIT A typical application circuit for the DES is shown in Figure15. This circuit shows the LMH0341 3 Gbps deserializer, al-ternately this could employ the LMH0041 or LMH0071 dese-rializers in lower data rate SMPTE applications. The RX interface between the DES and the host FPGA iscomposed of a 5-bit LVDS Data bus and its LVDS clock. Thisis a point-to-point interface. Line termination should be pro-vided by the FPGA device. If not, and external 100Ω resistormaybe used and should be located as close to the FPGA aspossible to minimize stub lengths. Pairs should be of equallength to minimize any skew impact. The LVDS clock (RX-CLK) uses both edges to transfer the data. An SMBus is also connected from the host FPGA to the DES.If the SMBus is shared, a chip select signal is used to selectthe device being addressed. The SCK and SDA signals re-quire a pull up resistor. The SMB_CS is driven by a GPOsignal from the FPGA. Depending on the FPGA I/O it may alsorequire a pull up unless it is a push / pull output. Depending upon the application, several other Host GPIOsignals maybe used. This includes the DVB_ASI and RE-SET input signals. If these pins are not used, then must betied off to the desired state. The LOCK signal maybe used tomonitor the DES. If it is unused, leave the pin as a NC (orroute to a test point). Note also in this circuit, the LMH0341 GPIO_1 pin has beenconfigured to provide the status of RXIN_1. When there is asignal present coming from the LMH0340, then RXIN_1 willbe selected. If that signal is lost, the input MUX will automat-ically switch over to provide the system reference black signalas the input from RXIN_0. The DES includes a SMPTE compliant cable driver for theLoopthrough function. While this is a differential driver, it iscommonly used single-endedly to drive 75 Ω coax cables.External 75 Ω pull up resistors are used to the 2.5V rail. Theactive output(s) also includes a matching network to meet therequired Output Return Loss SMPTE specification. While ap-plication specific, in general a series 75 Ω resistor shunted bya 6.8 nH inductor will provide a starting value to design with.The signal is then AC coupled to the cable with a 4.7 µF ca-pacitor. If the complementary output is not used, simply ter-minate it after its AC coupling capacitor to ground. This output(even though its inverting) may still be used for a loop backor 1:2 function due to the nature of the NRZI coding that the 15 www.national.com LMH0341, LMH0041, LMH0071, LMH0051SMPTE standards require. The output voltage amplitude ofthe cable driver is set by the RSET resistor. For single-endedapplications, an 8.06 kΩ resistor is connected between thispin and ground to set the swing to 800mV. The PLL loop filter is external for the SER. A capacitor is con-nected between the LF_CP and LF_REF pins. Typical valueis 30 nF. There are several configuration pins that requiring setting tothe proper level. The RSVD_H pins should be pulled High tothe 3.3V rail with a 5 kΩ resistor. Depending upon the appli-cation the DVB_ASI pin may be tied off or driven. There are three supply connections (see By Pass discussionand also Pin Descriptions for recommendations). The twomain supplies are the 3.3V rail and the 2.5V rail. There is alsoa 3.3V connection for the PLL circuitry. There are multiple Ground connections for the device. Themain ground connection for the SER is through the large cen-ter DAP pad. This must be connected to ground for properdevice operation. In addition, multiple other inputs are re-quired to be connected to ground as show in the figure andlisted in the Pin Description table. 30017210 FIGURE 15. Typical SMPTE Application Circuit www.national.com16 LMH0341, LMH0041, LMH0071, LMH005130017218 FIGURE 16. Typical CML Application Circuit (LMH0051) 17www.national.com LMH0341, LMH0041, LMH0071, LMH0051Register Descriptions the following table provides details on the device's configura-tion registers. DES Register Detail Table ADD 'hName00 Bits Field R/W Default Description device_identificaThe seven MSBs of this register define the SMBus address for the device. The default value is 0x58h,tionbut this may be overwritten. The LSB of this register must always be '0' Note that since the address is shifted over by one bit, some systems may address the 058h as 'B0h 7:10 01 reset device_idreserved r/w 058h0 SMBus Device ID If a '1' is written into the LSB of register 0x01h then the device will do a soft reset, restoring it's internalstate to the same as at powerup with the exception of the contents of register 0x00h, which if modifiedwill remain unchanged7:10 reservedsw_rst r/w 0'b Software Reset 02 GPIO_0 ConfigurationThis register configures GPIO_0. Note, if this pin is to be used as an input, then the output must beTRI-STATE (bit[0]=’0’) and if used as an output, then the input buffer must be disabled (bit[1]=’0’).7:4 GPIO_0_mode[3:0] r/w 0000'b 0000: GPout register0001: signal detect 00010:BIST Status0011: 0110: RX_SM_State[0]0111:ana divided raw dataall others: reserved 00: pullup and pulldown disabled01: pulldown enabled10: pullup enabled11: Reserved 0: input buffer disabled1: input buffer enabled0: output TRI-STATE1: output enabled 3:2 GPIO_0_ren[1:0] r/w01'b 10 03 GPIO_1 Configuration GPIO_0_sleepz GPout0 enable r/wr/w 0'b1'b This register configures GPIO_1. Note, if this pin is to be used as an input, then the output must beTRI-STATE (bit[0]=’0’) and if used as an output, then the input buffer must be disabled (bit[1]=’0’).7:4 GPIO_0_mode[3:0] r/w 0000'b 0000: POR 0001: GP_OUT[1]0010:signal detect 10011:cdr_lock0100: BIST Done0110: rx_sm_state[1] 0111:ana_0_retimed dataall others: reserved 00: pullup and pulldown disabled01: pulldown enabled10: pullup enabled11: Reserved 0: input buffer disabled1: input buffer enabled0: output TRI-STATE1: output enabled 3:2 GPIO_0_ren[1:0] r/w01'b 10 GPIO_0_sleepz GPout0 enable r/wr/w 0'b1'b www.national.com18 LMH0341, LMH0041, LMH0071, LMH0051ADD 'hName04 GPIO_2 Configuration BitsFieldR/WDefaultDescription This register configures GPIO_2. Note, if this pin is to be used as an input, then the output must beTRI-STATE (bit[0]=’0’) and if used as an output, then the input buffer must be disabled (bit[1]=’0’).7:4 GPIO_0_mode[3:0] r/w 0000'b 0000: GPout [2]register0001:Always ON clock0010: LVDS TX CLK0011:CDR_CLK0101: LFR error 0110:RX_SM_State[2] 0111: ana_raw_retimer_counterequalall others: reserved 00: pullup and pulldown disabled01: pulldown enabled10: pullup enabled11: Reserved 0: input buffer disabled1: input buffer enabled0: output TRI-STATE1: output enabled 3:2 GPIO_0_ren[1:0] r/w01'b 10 05 GP Input GPIO_0_sleepz GPout0 enable r/wr/w 0'b1'b If any of the GPIO pins are configured as inputs, then reading from this register provides the valueson those input pins7:3210 Reserved rrr Input data on GPIO 2Input data on GPIO 1Input data on GPIO 0 06GP Output If the GPIO ins are configured as General Purpose output pins, then writing to this register has theeffect of transferring the bits in this register to the output buffers of the GPIO pins.7:3210 Reserved r/wr/wr/w Output data on GPIO 2Output data on GPIO 1Output data on GPIO 0 07–0C0D Reserved DVB_ASI Idle_AWhen in DVB_ASI mode, idle characters are inserted into the datastream when there is no valid data to transmit. This character is recognized by the receiver. The default character is K28.5 but if desiredthat can be redefined via this register pair 7:07:21:0 Reserved r/w r/w 83 2 Data [7:0] Data[9:8] DVB_ASI Idle_BDVB_ASI idle character MSBs 0E 0F–1CReserved 19www.national.com LMH0341, LMH0041, LMH0071, LMH0051ADD 'hName1D Variant BitsFieldR/WDefaultDescription Reading from this register will return an 8 bit value which indicates which variant of the DES is beingaddressed7:65 ReservedLoop throughenablemode rr pin valueThis bit returns the state of the loop-through enable, and defaults to the same as the state of theLoopthru_EN pinpin valueReturns a two bit pattern which indicates the state that the device is in 00,01,10: Standard Video Mode11: DVB_ASI Mode returns the part type:00: LMH0341 01: LMH0041/LMH005110:LMH007111:Reserved 4:3r 21:0 ReservedVariant r 1E-1F20 ReservedControl 7:32 ReservedData Order r/w 0 Determines deserialization order —0: Expects LSB to be received first1:Expects MSB to be received first Writing a '1' to this bit forces a reset of the channelWriting a '1' to this bit will shut down several of thedigital processing sections of the product to savepower. If enabled by register 22, then this bit will override theRX_MUX_SEL pin. 00,01,10: Standard Operation11: DVB_ASI 10 Reset ChannelDigital Powerdown r/wr/w 00 21DVB_ASIThis register allows the device to be placed in DVB_ASI mode or standard operation mode7:543:21:0 ReservedRX_MUX_SELReservedDVB_ASI r/w r/w 0 0 22Override This register allows the user to control the DVB_ASI and input select functions via the SMBus interfacerather than the pin controls.7:54 ReservedRX_MUXControlOverrideReservedDVB_ASIOverride r/w 0 Writing a '1' to this register allows register 21 tocontrol the state of the input multiplexer — if the bitis set to '0' then the selection will be determined bythe state of the RX_MUX_SEL pin Writing a '1' to this register allows register 21 tocontrol the state of the DVB_ASI Select pin — if thebit is set to '0' then the selection will be determinedby the state of the DVB_ASI pin if '1' then thecontents of register 21 take precidence 3:10 23–26Reserved www.national.com20 LMH0341, LMH0041, LMH0071, LMH0051ADD 'hName27 LVDS Control 1 BitsFieldR/WDefaultDescription This register allows control of the LVDS output pins — using this register individual LVDS outputs canbe enabled or disabled, and the outputs can be switched to high output mode7 LVDS_VOD r/w 0 With a '0' the VOD of the LVDS output are asdescribed in the electrical characteristics table, writing a '1' to this bit generates a larger VODallowinglonger traces to be driven, and increasing total powerdissipation Writing a '1' to this bit allows the LVDS outputs to becontrolled via the SMBusEnables the RXCLK output driverEnables RX4 output driverEnables RX3 output driverEnables RX2 output driverEnables RX1 output driverEnables RX0 output driver Resets LVDS Block 1: RXCLK is a DDR clock 0: RXCLI is at a rate of DDR/2 Inverts the polarity of the RXCLK signal Each LSB adds 100ps delay to the RXCLK signalpath, allowing the setup and hold times to beadjusted. 6543210 28 LVDS Control 2 76543:2 LVDS ControlRXCLK EnableRX4 EnableRX3 EnableRX2 EnableRX1 EnableRX0 EnableReservedLVDS ResetRXCLK RateRXCLK InvertLVDS ClockdelayReserved r/wr/wr/wr/wr/wr/wr/w r/wr/wr/wr/w 0000000 01010'b More bits allowing control over the LVDS outputs 1:0 29–2A2B ReservedEvent Configuration Allows control over the counting of error events on the clock recovery PLL7:43 ReservedEvent CountSelect r/w 0 0: Select CDR Event counter for reading — eventsare counted for a loss of the RXCLK signal, or a lossof lock 1: Select data event counterResets CDR Event countresets data event counterenables event counters 210 2C2D ReservedError Monitor Reset CDRError CountReset LinkError Countenable count r/wr/wr/w 000 Controls Error Monitoring functions7:54321 ReservedAccumulateError Count8b10b errordisableclear eventcountselect errorcount r/wr/wr/wr/w 0000 Enable counting accumulation of errors When set, disables 8b10b errors from being counted,or from affecting the status of the LOCKpinWhen set, clears the number of errors in both thecurrent and previous state of the error countSelect which error count to display0: Number of errors in current run 1: Number of errors within the selected timingwindow Disable exiting NORMAL state when the number oferrors exceeds the error threshold 0 Normal ErrorDisable r/w0 21www.national.com LMH0341, LMH0041, LMH0071, LMH0051ADD 'hName2E Error Threshold Bits7:0 Field Error Threshold R/Wr/w Default0x10h Description Error threshold above which the device stops receiving data and transferring it to the RXOUT pins.Error threshold above which the device stops receiving data and transferring it to the RXOUT pins. Sets the error threshold LSBs 2FError ThresholdSets the error threshold MSBs Error Threshold r/w 00 30–3A3B ReservedData Rate This Register provides information about the rate at which the receive PLL is locked76:4 ReservedFreq Range r 111 001: 270 Mbps011: 1.485 Gbps110: 2.97 Gbps111: Unlocked 3:0 3C3D3E ReservedEvent StatusError Status 1 Reserved Error Counting register7:07:0 event countData ErrorCount 1Data ErrorCount 2 r/wr/w 00 count of errors that caused a loss of the linkNumber of errors in the data — LSB Error Count LSB 3FError Status 2Error Counting Register MSB7:0 r/w 0 Number of errors in the data — MSB www.national.com22 LMH0341, LMH0041, LMH0071, LMH0051Connection Diagrams 30017211 FIGURE 17. Connection Diagram for LMH0341 / LMH0041 / LMH0071 23www.national.com LMH0341, LMH0041, LMH0071, LMH005130017212 FIGURE 18. Connection Diagram for LMH0051 www.national.com24 LMH0341, LMH0041, LMH0071, LMH0051Ordering Information NSIDLMH0341SQLMH0341SQXLMH0341SQELMH0041SQLMH0041SQXLMH0041SQELMH0071SQLMH0071SQXLMH0071SQELMH0051SQLMH0051SQXLMH0051SQE HD / SD CML SD SMPTE, Loopthrough HD / SD SMPTE, Loopthrough Speed3G / HD / SD Feature SMPTE, Loopthrough Units per T&R1,0002,5002501,0002,5002501,0002,5002501,0002,500250 SQA48ASQA48ASQA48APackageSQA48A 25www.national.com LMH0341, LMH0041, LMH0071, LMH0051Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead QFN Plastic Quad PackageNS Package Number SQA48A www.national.com26 LMH0341, LMH0041, LMH0071, LMH0051Notes 27www.national.com LMH0341, LMH0041, LMH0071, LMH0051 3Gbps, HD, SD, DVB-ASI SDI Deserializer withLoopthrough and LVDS InterfaceNotes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products AmplifiersAudio Clock ConditionersData ConvertersDisplaysEthernetInterfaceLVDS Power Management Switching Regulators LDOs LED LightingPowerWise Serial Digital Interface (SDI)Temperature SensorsWireless (PLL/VCO) www.national.com/amplifierswww.national.com/audiowww.national.com/timingwww.national.com/adcwww.national.com/displayswww.national.com/ethernetwww.national.com/interfacewww.national.com/lvdswww.national.com/powerwww.national.com/switcherswww.national.com/ldowww.national.com/ledwww.national.com/powerwisewww.national.com/sdi www.national.com/tempsensorswww.national.com/wireless WEBENCHAnalog UniversityApp NotesDistributorsGreen CompliancePackaging Design Support www.national.com/webenchwww.national.com/AUwww.national.com/appnoteswww.national.com/contactswww.national.com/quality/greenwww.national.com/packagingwww.national.com/qualitywww.national.com/refdesignswww.national.com/feedback Quality and ReliabilityReference DesignsFeedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION(“NATIONAL”) PRODUCTS. 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