MEMORY存储芯片TMS320C6414TBGLZA6中文规格书

SPRS146N − FEBRUARY 2001 − REVISED MAY 2005DEVICE CONFIGURATIONS (CONTINUED)

Table 29. C6414, C6415, and C6416 Device Multiplexed Pins†

MULTIPLEXED PINSNAME

CLKOUT4/GP1‡

NO.AE6

DEFAULT FUNCTIONCLKOUT4

DEFAULT SETTINGGP1EN = 0 (disabled)

DESCRIPTION

These pins are software-configurable.To use these pins as GPIO pins, theGPxEN bits in the GPIO EnableRegister and the GPxDIR bits in theGPIO Direction Register must beproperly configured.

GPxEN = 1:GPx pin enabledGPxDIR = 0:GPx pin is an inputGPxDIR = 1:GPx pin is an outputTo use GP[15:9] as GPIO pins, the PCIneeds to be disabled (PCI_EN = 0), theGPxEN bits in the GPIO EnableRegister and the GPxDIR bits in theGPIO Direction Register must beproperly configured.

GPxEN 1:GPx pin enabledGPxEN = 1:

GPxDIR = 0:GPx pin is an inputGPxDIR = 1:GPx pin is an output

CLKOUT6/GP2‡AD6CLKOUT6GP2EN = 0 (disabled)

CLKS2/GP8‡GP9/PIDSELGP10/PCBE3GP11/PREQGP12/PGNTGP13/PINTAGP14/PCLKGP15/PRSTDX1/UXADDR4FSX1/UXADDR3FSR1/UXADDR2DR1/UXADDR1CLKX1/URADDR4CLKS1/URADDR3CLKR1/URADDR2CLKX2/XSP_CLKDR2/XSP_DIDX2/XSP_DOHD[31:0]/AD[31:0]HAS/PPARHCNTL1/PDEVSELHCNTL0/PSTOPHDS1/PSERRHDS2/PCBE1HR/W/PCBE2HHWIL/PTRDYHINT/PFRAMEHCS/PPERRHRDY/PIRDY†

AE4M3L2F1J3G4F2G3AB11AB13AC9AF11AB12AC8AC10AC2AB3AA2

§

CLKS2GP8EN = 0 (disabled)

None

GPxEN = 0 (disabled)GPEN 0 (dibld)PCIEN = 0 (disabled)†PCI_EN = 0 (disabled)

DX1FSX1FSR1DR1CLKX1CLKS1CLKR1CLKX2DR2DX2HD[31:0]HASHCNTL1HCNTL0HDS1HDS2HR/WHHWIL (HPI16 only)HINTHCSHRDYPCI_EN = 0 (disabled)PCIEN 0 (disabled)†

By default, HPI is enabled upon reset

(PCI is disabled). (PCI is disabled)

To enable the PCI peripheral an externalpullup resistor (1 kpp(Ω) must be provided)p

on the PCI_EN pin (setting PCI_EN = 1 h PCIEN i (i PCIEN 1at reset)at reset).

UTOPIA_EN (BEA11) = 0UTOPIAEN (BEA11) 0

(disabled)†

By default, McBSP1 is enabled uponreset (UTOPIA is disabled).()T bl To enable the UTOPIA peripheral, anh UTOPIA ihl external pullup resistor (1 kΩ) must beprovided on the BEA11 pin (settingprovided on the BEA11 pin (settingUTOPIA_EN = 1 at reset)._)

T3R1T4T1T2P1R3R4R2P4

For the C6415 and C6416 devices, all other standalone UTOPIA and PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled

[UTOPIA_EN (BEA11) = 0 or PCI_EN = 0].

‡The C6414 device does not support the PCI and UTOPIA peripherals. These are the only multiplexed pins on the C6414 device, all other pinsare standalone peripheral functions and are not muxed.

§For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.

TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS146N − FEBRUARY 2001 − REVISED MAY 2005Terminal Functions (Continued)

SIGNALNAMEBCE3BCE2BCE1BCE0BBE1BBE0BPDTBHOLDABHOLDBBUSREQ

NO.A13C12B12A12D13C13E12E13B19E14

TYPE†

IPD/IPU‡IPUIPUIPUIPUIPUIPUIPUIPUIPUIPU

EMIFB memory space enables

•Enabled by bits 26 through 31 of the word address

•Only one pin is asserted during any external data access

EMIFB byte-enable control

•Decoded from the low-order address bits. The number of address bits or byte enablesused depends on the width of external memoryused depends on the width of external memory.•Byte-write enables for most types of memory

•Can be directly connected to SDRAM read and write mask signal (SDQM)EMIFB peripheral data transfer, allows direct transfer between external peripheralsEMIFB (16-BIT) − BUS ARBITRATION||kOIO

EMIFB hold-request-acknowledge to the hostEMIFB hold request from the hostEMIFB bus request output

EMIFB external input clock. The EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)is selected at reset via the pullup/pulldown resistors on the BEA[15:14] pins.BECLKIN is the default for the EMIFB input clock.

EMIFB output clock 2. Programmable to be EMIFB input clock (BECLKIN, CPU/4 clock, orCPU/6 clock) frequency divided by 1, 2, or 4.

EMIFB output clock 1 [at EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) frequency].

EMIFB asynchronous memory read-enable/SDRAM column-address strobe/programmablesynchronous interface-address strobe or read-enable

•For programmable synchronous interface, the RENEN field in the CE Space SecondaryControl Register (CExSEC) selects between BSADS and BSRE:If RENEN = 0, then the BSADS/BSRE signal functions as the BSADS signal.If RENEN = 1, then the BSADS/BSRE signal functions as the BSRE signal.EMIFB asynchronous memory output-enable/SDRAM row-address strobe/programmablesynchronous interface output-enable

EMIFB asynchronous memory write-enable/SDRAM write-enable/programmable synchro-nous interface write-enable

EMIFB synchronous memory output enable for BCE3 (for glueless FIFO interface)EMIFB asynchronous memory ready input

DESCRIPTION

EMIFB (16-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY||kO/ZO/ZO/ZO/ZO/ZO/ZO/Z

EMIFB (16-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL||kBECLKINBECLKOUT2BECLKOUT1

A11D11D12

IO/ZO/Z

IPDIPDIPD

BARE/BSDCAS/BSADS/BSREBAOE/BSDRAS/BSOEBAWE/BSDWE/BSWEBSOE3BARDY

†‡

A10O/ZIPU

B11C11E15E11

O/ZO/ZO/ZI

IPUIPUIPUIPU

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the oppositesupply rail, a 1-kΩ resistor should be used.)

||These C64x™ devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signalwhereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas ofdiscussion, the prefix “A” or “B” may be omitted from the signal name.

kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.